High-k gate dielectric and method of manufacture

ABSTRACT

A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.

TECHNICAL FIELD

The present invention relates generally to a system and method offorming a high-k material, and more particularly to a system and methodfor forming a high-k gate dielectric in a metal-oxide semiconductorfield-effect transistor.

BACKGROUND

With the scaling of integrated circuits, applications require anincreasingly faster speed. This puts a requirement on themetal-oxide-semiconductor (MOS) devices, demanding that the MOS devicesswitch faster. As is known in the art, to increase the speed of MOSdevices, high dielectric constant values (k values) of the gatedielectrics are desired. Since conventional silicon oxide, which has a kvalue of about 3.9, cannot satisfy such a requirement, high-k dielectricmaterials, which include oxides, nitrides, and oxynitrides, areincreasingly used.

Such a MOS device 100 is illustrated in FIG. 1, which has a substrate101 with isolation regions 103, a gate dielectric 105, a gate electrode107, source/drain regions 109, and spacers 111. In this device 100 thegate dielectric 105 is formed from a high-k dielectric material in orderto increase the switching speed of the device.

However, when the gate electrode 107 is formed directly over the high-kmaterial in the gate dielectric 105, an effect known as Fermi-levelpinning occurs which can reduce the switching speed of the device 100.This “pinning” of the Fermi layer along the interface of the gatedielectric 105 and the gate electrode 107 is the result of two causes.The first cause is dangling bonds (broken covalent bonds) along the edgeof the high-k material that will bond with the deposited gate electrodeand form a “pinned” interface state. The second cause is a lack ofoxygen bonds along the interface and the high-k material. Both of thesecauses have an effect on the Fermi-level pinning of the interface,thereby decreasing the efficiency of the device as a whole.

Accordingly, what is needed is a device and method of formation toeither reduce the dangling bonds of the high-k material or increase theamount of oxygen along the interface.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, andtechnical advantages are generally achieved, by preferred embodiments ofthe present invention which reduce the dangling bonds of the high-kmaterial that are available to bond with the subsequent conductivematerial, and also increase the amount of oxygen along the interface ofthe high-k dielectric material and the gate electrode.

In accordance with a preferred embodiment of the present invention, asemiconductor device comprises a substrate with a high-k dielectricmaterial over the substrate. Over the high-k dielectric material, anoxidized silicon-rich film is located, and a conductive material islocated over the silicon-rich film.

In accordance with another preferred embodiment of the presentinvention, a semiconductor device comprises a substrate and a high-kdielectric material over the substrate. On the high-k dielectricmaterial, a film comprising silicon and nitrogen is located, and aconductive layer is located over the film.

In accordance with yet another preferred embodiment of the presentinvention, a transistor is formed with a substrate, a gate stack on thesubstrate, source/drain regions in the substrate on opposing sides ofthe gate stack, and spacers formed on the sidewalls of the gate stack.The gate stack comprises a layer of high-k material over the substrate,a film of material that comprises silicon and either nitrogen or oxygen,and a conductive layer over the film.

An advantage of a preferred embodiment of the present invention isreduced or eliminated Fermi-level pinning at the interface of the high-kdielectric and the gate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a transistor as is known in the prior art; and

FIGS. 2-8 illustrate steps in the process of forming a high-k gatedielectric in accordance with an embodiment of the present invention.

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the embodiments andare not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to preferredembodiments in a specific context, namely a gate dielectric in ametal-oxide semiconductor field effect transistor. The invention mayalso be applied, however, to other devices that benefit from a high-kdielectric material.

With reference now to FIG. 2, there is shown a substrate 201 withshallow trench isolations (STIs) 203 formed therein. The substrate 201may comprise bulk silicon, doped or undoped, or an active layer of asilicon-on-insulator (SOI) substrate. Generally, an SOI substratecomprises a layer of a semiconductor material such as silicon,germanium, silicon germanium, SOI, silicon germanium on insulator(SGOI), or combinations thereof. Other substrates that may be usedinclude multi-layered substrates, gradient substrates, or hybridorientation substrates.

The STIs 203 are generally formed by etching the substrate 201 to form atrench and filling the trench with a dielectric material as is known inthe art. Preferably, the STIs 203 are filled with a dielectric materialsuch as an oxide material, a high-density plasma (HDP) oxide, or thelike, formed by conventional methods known in the art.

A base oxide layer 205 may be formed over the substrate 201. In thepreferred embodiment, base oxide layer 205 is formed by submergingsubstrate 201 into a solution, which contains de-ionized water and ozone(O₃). Such a solution is often denoted as DiO₃. The DiO₃ solution ispreferably ultra-diluted, containing O₃ of between about 1 part permillion (ppm) and about 100 ppm, and more preferably between about 1 ppmand about 10 ppm. The oxidation is preferably performed at roomtemperature, for example, about 25° C., although higher or lowertemperatures can be used. The preferred process time is about 10 secondsto about 30 seconds. However, alternative methods of formation, such assubjecting the silicon-rich film 401 to an oxidizing environment such assteam or oxygen-containing ambient at a room temperature of about 600°C. to about 1,100° C., could alternatively be utilized.

Base oxide layer 205 preferably has a thickness of less than about 10 Å,and more preferably between about 5 Å to about 7 Å. The thickness of thebase oxide layer 205 can be controlled by adjusting the processconditions such as time, temperature, etc. As is commonly perceived,given a process time, the thickness of the base oxide layer 205 may beaffected by the process temperature. A low temperature tends to causeslower oxide formation, but the oxide thickness tends to be thin. Theoptimal process temperature and process time may be determined byroutine experiments.

FIG. 3 illustrates the formation of a high-k dielectric layer 301 on thebase oxide layer 205, as is shown in FIG. 5. In the preferredembodiment, the high-k dielectric layer 301 includes hafnium oxide(HfO₂) or else a silicate oxide such as HfSiO_(x). In alternativeembodiments, the high-k dielectric layer 301 includes otherhafnium-containing materials such as HfZrO_(x), HfAlO_(x), HfLaO_(x),HfO₂, HfTiO_(x), HfTaO_(x), HfTiTaO_(x), and combinations thereof. Inyet other embodiments, high-k dielectric layer 301 includes metal oxidessuch as LaO₃, ZrO₂, Al₂O₃, Ta₂O₅, TiO₂, and combinations thereof.Preferably, the k value of the high-k dielectric layer 301 is greaterthan about 7. Conventionally, the high-k dielectric layer 301 preferablyhas a thickness of at least 30 Å. Otherwise, the leakage current throughthe high-k dielectric layer 301 may be significant. In the preferredembodiment, however, with higher quality and a more amorphous structure,the thickness of the high-k dielectric layer 301 can be 30 Å or less, oreven 20 Å or less, without causing a significant leakage current. Itshould be appreciated that the high-k dielectric layer 301 may also havea thickness of greater than about 20 Å, or even about 30 Å or more.

The preferred formation method of high-k dielectric layer 301 is atomiclayer deposition (ALD). However, other commonly used methods such asplasma enhanced chemical vapor deposition (PECVD), low-pressure chemicalvapor deposition (LPCVD), metal-organic chemical vapor deposition(MOCVD), plasma enhanced atomic layer deposition (PEALD), and the like,can also be used. High-k dielectric layer 301 is preferably formed at alow temperature, for example, lower than about 500° C., and morepreferably lower than about 350° C., and even more preferably lower thanabout 250° C. The low temperature will prevent the re-growth of theinterfacial oxide layer between substrate 201 and the overlying baseoxide layer 205, particularly when oxygen is preserved during theformation of high-k dielectric layer 301.

FIG. 4 illustrates the formation of a silicon-rich film 401 on thehigh-k dielectric layer 301. The silicon-rich film 401 is preferablyformed in the same manner as the high-k dielectric layer 301, forexample, ALD and the like, as described above with reference to FIG. 3.However, precursors for the formation of silicon would be used insteadof precursors for the high-k dielectric layer 301. In an embodiment inwhich a silicate oxide is being formed as the high-k dielectric layer301, the silicon-rich film 401 is preferably formed as the last step inthe formation of the high-k dielectric layer 301 by reducing theprecursors used in the ALD of the high-k dielectric layer 301 until onlythe silicon precursors are present to deposit the silicon-rich film 401onto the high-k dielectric layer 301.

In an embodiment in which a metal oxide is used to form the high-kdielectric layer 301, the formation of the high-k dielectric layer 301is completed prior to the formation of the silicon-rich film 401. Thesilicon-rich film 401 is then preferably formed through a separateprocess such as ALD with silicon precursors. However, when a metal oxideis used as the high-k material for the high-k dielectric layer 301, partof the silicon that is deposited immediately adjacent to the metal oxidehigh-k dielectric layer 301 will react with an upper portion of themetal oxide high-k dielectric layer 301 to form a metal oxide silicate(not shown) between the high-k dielectric layer 301 and the silicon-richfilm 401.

FIG. 5 illustrates the oxidation of the silicon-rich film 401. Byoxidizing the silicon-rich film 401 after its formation, the material inthe high-k dielectric material (either metal oxide or silicate oxide)will react and bond to the oxygen and will not bond to the subsequentlydeposited gate electrode (discussed below with reference to FIG. 6).This bonding reduces the Fermi-level pinning that would otherwise occurat this interface if the silicon-rich film 401 is not formed.

The silicon-rich film 401 may be oxidized in a similar manner as thesubstrate 201 was oxidized to form the base oxide layer 205 asreferenced above with respect to FIG. 2. In other words, thesilicon-rich film 401 may be either chemically or thermally oxidized.Preferably, the oxidation of the silicon-rich film 401 is continueduntil the silicon-rich film 401 is completely oxidized.

In an embodiment in which the high-k dielectric layer 301 is a silicateoxide, the oxidation of the silicon-rich film 401 will result in abonding structure downward from the oxidized silicon-rich film 401 tothe high-k dielectric layer 301 that will substantially beSi—Si—O—Si—O—Si(M_(X))—Si(M_(X)), where Si(M_(X)) is the silicate oxide.In an embodiment in which the high-k dielectric layer 301 is a metaloxide, the oxidation of the silicon-rich film 401 will result in abonding structure downward from the oxidized silicon-rich film 401 tothe high-k dielectric layer 301 that will substantially beSi—Si—O—Si—O—Si(M_(X))-M_(X), where M_(X) is the metal oxide high-kdielectric material and Si(M_(X)) is the metal oxide silicate formed onthe surface of the high-k dielectric layer 301.

Alternatively to oxidation, a nitridation of the silicon-rich film 401could be utilized to bond to the material of the high-k dielectric layer301 and prevent the high-k material from bonding to the gate electrodematerial. Preferably, the nitridation of the silicon-rich film 401 maybe performed by exposing the silicon-rich film 401 to anammonia-containing environment at about 600° C. to about 900° C. andabout 500 Pa to about 8,000 Pa. Other methods, such as exposing thesilicon-rich film 401 to a nitrogen-containing plasma environment at atemperature of about 20° C. to about 100° C., a pressure of about 1 Pato about 10 Pa, and an exciting frequency of about 13.56 MHz and about100 to about 1,000 W, could alternatively be used. Preferably, thenitridation of the silicon-rich film 401 is continued until thesilicon-rich film 401 is fully nitrided without any dangling bond.

In an embodiment in which the high-k dielectric layer 301 is a silicateoxide and nitridation is performed, the nitridation of the entiresilicon-rich film 401 will result in a bonding structure downward fromthe nitridized silicon-rich film 401 to the high-k dielectric layer 301that will substantially be Si—Si—N—Si—O(N)—Si(M_(X))—Si(M_(X)), whereSi(M_(X)) is the silicate oxide material of the high-k dielectric layer301 and the O(N) is an oxynitride. In an embodiment in which the high-kdielectric layer 301 is a metal oxide, the nitridation of the entiresilicon-rich film 401 will result in a bonding structure downward fromthe nitridized silicon-rich film 401 to the high-k dielectric layer 301that will substantially be Si—Si—N—Si—O(N)—Si(M_(X))-M, where Si(M_(X))is the metal silicate oxide formed on the surface of the high-kdielectric layer 301, M is the metal oxide material of the high-kdielectric layer 301, and O(N) is an oxynitride.

The deposition and subsequent treatment of the silicon-rich film 401reduces the number of dangling bonds that are located along the surfaceof the high-k dielectric layer 301. With the reduction of these danglingbonds, fewer atoms of the high-k material layer 401 will react and bondwith the material of the gate electrode, thereby reducing theFermi-level pinning that would occur absent the treated silicon-richfilm 401. Further, with the oxidation of the silicon-rich film 401,there will be a reduced shortage of oxygen bonds at the interface,thereby further reducing the amount of Fermi-level pinning.

FIG. 6 illustrates the formation of a gate electrode layer 601 on thesilicon-rich layer 401. The gate electrode layer 601 preferablycomprises a conductive material, such as polysilicon, a metal (e.g.,tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium,ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide,nickel silicide, tantalum silicide), a metal nitride (e.g., titaniumnitride, tantalum nitride), doped poly-crystalline silicon, otherconductive materials, or a combination thereof. The gate electrode layer601 is preferably formed to have a thickness in the range of about 100 Åto about 2,500 Å, but more preferably about 600 Å.

The process used to form the gate electrode layer 601 is preferablycontrolled so that the oxygen-high-k material bonds (if the silicon-richlayer 401 was oxidized) or the nitrogen-high-k material bonds (if thesilicon-rich layer 401 was nitridized) are not broken. If these bondsare broken during the formation of the gate electrode layer 601, thehigh-k material could then bond with atoms from the gate electrode layer601, thereby creating the very Fermi-level pinning that is to beavoided.

As such, the gate electrode layer 601 is preferably polysilicon formedthrough physical vapor deposition (PVD). PVD is preferred because theharsh reducing environments that are required by some of the othermethods of formation may actively break the bonds that were formedduring the nitridation or oxidation processes, leaving the material inthe high-k dielectric layer 401 free to bond with the deposited gateelectrode layer 601, which is to be avoided. PVD, without as harsh areducing atmosphere, will not substantially break these bonds, thepreferred bonding structures as laid out above with respect to FIG. 5will remain intact, and the gate electrode layer 601 will be formed onthe silicon rich film 401.

However, while preferred, PVD is not the only method that may be used toform the gate electrode layer 601 and still retain some of thebeneficial properties of the present invention. Other methods, such asCVD or LPCVD, could alternatively be used if the process parameters arechosen so as not to remove all of the oxygen or nitrogen that is bondedto the material in the high-k dielectric layer 301. For example, duringCVD the process temperature should remain below about 580° C. in orderto avoid breaking the bonds.

If these other processes are performed in a reducing atmosphere thatincludes such precursors as elemental hydrogen (H₂), then some of thenitrogen or oxygen atoms that are bonded between the silicon-rich film401 and the material of the high-k dielectric layer 301 may be removed.However, there will still be some beneficial effects as long as theprocess conditions do not remove all of the nitrogen or oxygen and alsodo not break the metal silicate bonds, if present, in the material ofthe high-k dielectric layer 301.

In an embodiment in which the high-k dielectric layer 301 is a silicateoxide, the silicon-rich layer 401 has been oxidized, and the gateelectrode layer 601 is formed through a controlled process involving areducing atmosphere, the final bonding structure downward from theoxidized silicon-rich film 401 to the high-k dielectric layer 301 willsubstantially be Si—Si—O—Si—Si(M_(X))—Si(M_(X)), where Si(M_(X)) is thesilicate oxide. In an embodiment in which the high-k dielectric layer301 is a metal oxide, the silicon-rich layer 401 has been oxidized, andthe gate electrode layer 601 is formed through a controlled processinvolving a reducing atmosphere, the final bonding structure downwardfrom the oxidized silicon-rich film 401 to the high-k dielectric layer301 will substantially be Si—Si—O—Si—Si(M_(X))-M_(X), where M_(X) is themetal oxide and Si(M_(X)) is the metal oxide silicate formed on thesurface of the high-k dielectric layer 301.

In an embodiment in which the high-k dielectric layer 301 is a silicateoxide, the silicon-rich layer 401 has been nitridized, and a controlledprocess with a reducing atmosphere is used to form the gate electrodelayer 601, the final bonding structure downward from the silicon-richfilm 401 to the high-k dielectric layer 301 may substantially beSi—Si—N—Si—Si(M_(X))—Si(M_(X)), where Si(M_(X)) is the silicate oxidematerial of the high-k dielectric layer 301. In an embodiment in whichthe high-k dielectric layer 301 is a metal oxide, the silicon-rich film401 is nitridized, and a controlled process with a reducing atmosphereis used to form the gate electrode layer 601, the final bondingstructure downward from the nitridized silicon-rich film 401 to thehigh-k dielectric layer 301 will substantially beSi—Si—N—Si—Si(M_(X))-M_(X), where Si(M_(X)) is the metal silicate oxideformed on the surface of the high-k dielectric layer 301 and M is themetal oxide material of the high-k dielectric layer 301.

FIG. 7 illustrates the formation of a gate stack 701 from the gateelectrode layer 601, the silicon-rich film 401, the high-k dielectriclayer 301, and the base oxide layer 205. The gate stack 701 ispreferably formed by the deposition and patterning of a photoresistlayer (not shown) over the gate electrode layer 601. The material notcovered by the patterned photoresist layer is then removed through aprocess such as an etch until the substrate 201 is substantiallyexposed.

FIG. 8 illustrates the formation of spacers 801 and source/drain regions803 in order to complete the formation of the device 800. The spacers801 are formed on the sidewalls of the gate stack 701. The spacers 801are typically formed by blanket depositing a spacer layer (not shown) onthe previously formed structure. The spacer layer preferably comprisesSiN, oxynitride, SiC, SiON, oxide, and the like, and is preferablyformed by commonly used methods such as chemical vapor deposition (CVD),plasma enhanced CVD, sputter, and other methods known in the art. Thespacer layer is then patterned to form the spacers 801, preferably byanisotropically etching to remove the spacer layer from the horizontalsurfaces of the structure.

Source/drain regions 803 are formed in the substrate 201 on opposingsides of the gate stack 701. In an embodiment in which the substrate isan n-type substrate, the source/drain regions 803 are preferably formedby implanting appropriate p-type dopants such as boron, gallium, indium,or the like. These source/drain regions 803 are implanted using the gatestack 701 and the gate spacers 801 as masks.

It should be noted that one of ordinary skill in the art will realizethat many other processes, steps, or the like may be used to form thesesource/drain regions 803. For example, one of ordinary skill in the artwill realize that a plurality of implants may be performed using variouscombinations of spacers and liners to form source/drain regions having aspecific shape or characteristic suitable for a particular purpose. Anyof these processes may be used to form the source/drain regions 803, andthe above description is not meant to limit the present invention to thesteps presented above.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. For example,there are multiple methods for the deposition of some of the materialsas the structure is being formed. Any of these deposition methods thatachieve substantially the same result as the corresponding embodimentsdescribed herein may be utilized according to the present invention.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

1. A method for manufacturing a semiconductor device, the methodcomprising: providing a substrate; forming a high-k dielectric layerover the substrate; forming a silicon-rich semiconductor film over thehigh-k dielectric layer; treating the silicon-rich semiconductor film atleast in part through the introduction of impurities that bond to thehigh-k dielectric layer; and forming a conductive layer over thesilicon-rich semiconductor film; wherein an oxide layer is formed on thesubstrate prior to the forming of the high-k dielectric layer.
 2. Themethod of claim 1, wherein the treating the silicon-rich semiconductorfilm comprises at least in part oxidizing the silicon-rich semiconductorfilm.
 3. The method of claim 1, wherein the treating the silicon-richsemiconductor film comprises at least in part nitridizing thesilicon-rich semiconductor film.
 4. The method of claim 1, wherein theforming the conductive layer over the silicon-rich semiconductor film isperformed at least in part through physical vapor deposition.
 5. Themethod of claim 1, further comprising: removing portions of the high-kdielectric layer, the silicon-rich semiconductor film, and theconductive layer to form a gate stack, the gate stack comprisingsidewalls; forming source/drain regions in the substrate on opposingsides of the gate stack; and forming spacers on the sidewalls of thegate stack.
 6. The method of claim 1, wherein the high-k dielectriclayer includes a number of dangling bonds, and wherein the treating thesilicon-rich semiconductor film is carried out in a manner that forms abonding structure between the impurities and the dangling bonds.
 7. Themethod of claim 6, wherein the forming the conductive layer is carriedout in a manner so that the bonding structure between the impurities andthe dangling bonds remains intact after the conductive layer is formed.8. A method for manufacturing a semiconductor device, the methodcomprising: providing a substrate; forming a layer of high-k dielectricmaterial over the substrate; forming a semiconductor film over the layerof high-k dielectric material, the semiconductor film comprising mostlysilicon; introducing impurities into the semiconductor film, at least aportion of the impurities bonding to the high-k dielectric material; andforming a layer of conductive material over the semiconductor film;wherein an oxide layer is formed on the substrate prior to the formingof the layer of high-k dielectric material.
 9. The method of claim 8,wherein the introducing the impurities is done at least in part byintroducing one of oxygen and nitrogen.
 10. The method of claim 8,wherein the forming the layer of conductive material over thesemiconductor film is performed at least in part through physical vapordeposition.
 11. The method of claim 8, further comprising: removingportions of the layer of high-k dielectric material, the semiconductorfilm, and the layer of conductive material to form a gate stack, thegate stack having sidewalls; forming source/drain regions in thesubstrate on opposing sides of the gate stack; and forming spacers onthe sidewalls of the gate stack.
 12. The method of claim 8, wherein thehigh-k dielectric material comprises a silicate.
 13. The method of claim8, wherein the high-k dielectric material comprises a metal.
 14. Themethod of claim 8, wherein a number of dangling bonds are located at aninterface between the high-k dielectric material and the semiconductorfilm, and wherein the introducing the impurities is carried out so thata portion of the dangling bonds are bonded to the semiconductor film,thereby reducing the number of dangling bonds.
 15. A method formanufacturing a transistor, the method comprising: providing a substratewith isolation regions formed therein; forming a layer of high-kmaterial over the substrate, the high-k material having a plurality ofdangling bonds; forming a film over the layer of high-k material, thefilm being a semiconductor material and comprising mostly silicon;treating the film in a manner that causes a portion of the danglingbonds to bond to the treated film; forming a gate electrode layer overthe treated film; removing portions of the layer of high-k material, thetreated film, and the gate electrode layer to form a gate stack; formingsource/drain regions in the substrate on opposing sides of the gatestack; and forming spacers on the sidewalls of the gate stack; whereinan oxide layer is formed on the substrate prior to the forming of thelayer of high-k material.
 16. The method of claim 15, wherein thetreating the film comprises at least in part oxidizing the film.
 17. Themethod of claim 15, wherein the treating the film comprises at least inpart nitridizing the film.
 18. The method of claim 15, wherein thehigh-k dielectric material comprises a silicate.
 19. The method of 15,wherein the forming the gate electrode is carried out in a manner sothat the dangling bonds that are bonded to the treated film are notbroken.
 20. The method of claim 19, wherein the forming the gateelectrode is carried out using one of a physical vapor depositionprocess and a chemical vapor deposition process having a processtemperature less than about 580 degrees Celsius.